[Domestic Virtual Instruments] Design of a Dual-Channel 6.4GSPS High-Speed Data Acquisition Module Based on FPGA+JESD204B Clock (Part 2) Research on JESD204B Link Establishment and Synchronization Process

Design of Acquisition and Data Reception Circuit Based on JESD204B

This chapter will focus on the implementation of dual-channel high-speed data acquisition based on the JESD204B high-speed data transmission interface. First, an overview of the JESD204B protocol and interface structure will be provided. Then, the process of JESD204B link establishment and synchronization will be investigated. Next, a multi-device synchronization scheme based on JESD204B Subclass 1 will be studied. Finally, the design for dual-channel synchronous acquisition and data reception, including clock, acquisition, and data reception design, will be completed.

3.1 JESD204B Protocol Overview

To address the increasing data throughput of high-sampling-rate, high-resolution data converters, the JEDEC association developed JESD204, a high-speed serial communication protocol for data converters and logic devices, and has continuously updated and revised it. Among them, JESD204B, the second revision of the JESD204 series protocol, is widely used by major well-known device manufacturers (such as ADI, TI) in high-speed data converters.

Compared to the previous two versions, JESD204B first increased