[Domestic Virtual Instrument] Design of a Dual-Channel 6.4GSPS High-Speed Data Acquisition Module Based on FPGA and JESD204B Clocking (Part 1) Overall Scheme

This chapter will analyze and determine the design scheme for the high-speed data acquisition module based on its performance requirements. It will then analyze data storage and speed requirements to propose a high-speed, large-capacity data storage solution. The overall design scheme for the dual-channel high-speed data acquisition module will be completed, and logic device selection will be provided by integrating the acquisition, storage, and AXIe interface requirements.

2.1 High-Speed Data Acquisition Module Specifications and Scheme Analysis

2.1.1 High-Speed Data Acquisition Specifications

The main technical specifications for the high-speed data acquisition module based on the AXIe test bus platform are as follows:

1. Maximum Sampling Rate: 6.4 GSPS

2. ADC Resolution: 12 bits

3. Number of Channels: 2

4. Analog Input Bandwidth: 1 GHz

5. Coupling: DC

6. Input Signal Amplitude: 125 mV, 250 mV, 500 mV, 1 V

7. Signal-to-Noise Ratio (SNR): 54 dB @ 380 MHz

8. Storage Depth: 2 Gpts

9. Transmission: Supports PCIe 2.0 version, four-lane, 5.0 Gbps interface protocol as per AXIe