A Design Solution for a High-speed Industrial Camera with RK3399+MIPI+FPGA (Part 3)
4 Design of the Software System for the MIPI Interface Embedded Platform Camera 4.1 Introduction to the FPGA Development Environment 4.1.1 Introduction to Development Languages Common FPGA development languages include Verilog HDL and VHDL. The suffix HDL stands for Hardware Description Language. Unlike C/C++ familiar from traditional software development, the biggest feature of hardware description languages is parallel execution, meaning all descriptive statements are executed concurrently at the same time. This is significantly different from the sequential execution of C/C++. This also leads to the high execution efficiency of FPGAs. In certain high-speed, low-latency fields, Verilog HDL and VHDL play a significant role. Verilog HDL is more commonly used in the domestic market. At the same time, Verilog HDL is divided into three description levels from high to low: behavioral level, RTL level, and structural level. In short, Verilog HDL statements describing functional states are processed by subsequent development platforms to generate corresponding gate-level circuits, and then system performance is further improved through layout and routing optimization. 4.1.2 Introduction to Development Platforms The primary development platform for Spartan-6 series chips is Xilinx's Integrated Software Environment (ISE) [39]. Subsequently, Xilinx also released a newer FPGA development environment, Vivado. However, Vivado has a larger software footprint, more complex compilation conditions, and higher PC performance requirements. This results in ISE having faster compilation speeds under the same conditions, effectively shortening the project development cycle. Furthermore, Vivado does not support Spartan-6 chips and earlier series. The detailed design flow can be divided into input, verification, synthesis, implementation, and download [40]. Corresponding to the description levels of Verilog HDL, this well reflects the hierarchical nature of engineering design. In the input stage, RTL-level description code is entered in a text editor. Further, during the verification process, simulation