Overview

Both commercial and open-source EtherCAT masters implement master functionality using software, with their performance largely depending on the PC's performance and the operating system's real-time capabilities. Xinmai, however, implements the EtherCAT protocol layer using pre-programmed FPGA logic, allowing customers to use it as a dedicated chip.

The EtherCAT max10 chip implements the standard EtherCAT master protocol, utilizing a standard general-purpose parallel bus interface that can connect to and control any CPU. It supports ARM or x86 processor platforms. It provides reference software code, API functions, XML file system initialization, and other software. It can be used for controlling any standard EtherCAT motors and I/O devices.

Features

⦁ Supports running EtherCAT master on bare-metal programs on ARM processors, without an operating system; ⦁ Supports x86 processors and PCIe interface, providing reference code for drivers and applications under Linux (with Xenomai real-time kernel); ⦁ User-friendly system debugging interface; ⦁ Low CPU load, enabling high real-time performance EtherCAT master communication quickly, regardless of high-end or low-end processors; ⦁ Strong synchronization performance between master and slave, with synchronization time jitter much less than 1us (50ns measured on 4 axes); ⦁ Short cycle time, easily achieving a communication cycle of 31.25us (a 62.5us cycle time can be achieved for 4 axes); ⦁ Easy system configuration via XML files, supporting a large number of slave connections.

Performance Comparison