1 Evaluation Board Introduction

(1) Based on TI KeyStone C66x multi-core fixed-point/floating-point DSP TMS320C665x + Xilinx Artix-7 FPGA processors; (2) The TMS320C665x has a clock frequency of 1.0G/1.25GHz, with a single-core computing capability of up to 40G MACS and 20G FLOPS. The FPGA XC7A100T features 101K logic cells and 240 DSP Slices; (3) The TMS320C665x connects with the FPGA via communication interfaces such as uPP, EMIF, I2C, PCIe, and SRIO, with PCIe and SRIO each supporting a maximum transmission speed of 5 GBaud per lane; (4) The FPGA acquisition card supports dual-channel 250MSPS*12Bit high-speed, high-precision ADC, and one channel 175MSPS*12Bit high-speed, high-precision DAC, meeting diverse data acquisition needs; (5) Supports Gigabit Ethernet port for connecting industrial network cameras, and also supports common interfaces such as I2C, SPI, UART, and McBSP; (6) Supports expansion modules such as CameraLink input/